SynaptiCAD Online Tutorials

General Design Tutorials

The Basic Drawing and Timing Analysis Tutorial explains the basic timing diagram editing environment: how to set the base time unit and the display time unit of a timing diagram; how to draw and edit signals, delays, and setups; and how to perform time measurements. This tutorial is essential to anyone evaluating or learning to use any SynaptiCAD product.

The Interactive HDL Simulation Tutorial explores the various time saving techniques of generating waveforms using equations. This tutorial explains how the Interactive HDL Simulator can simulate Boolean Equations with delays, register and latched signals, and behavioral Verilog code. It also demonstrates how instant resimulations can be performed when input waveforms are modified, so that tedious calculations, once done by hand, are now automatically generated.

The Waveform Generation and Bus Tutorial demonstrates techniques for working with multiple bit signals. These techniques include generating the waveforms and automatically labeling those waveforms using equations. This tutorial also covers how to create Virtual, Group, and Simulated buses for solving different design problems. These features augment the drawing environment and provide a quick way to generate signals without having to draw each signal transition.

The Parameter Display Tutorial demonstrates different methods for controlling the information that is displayed by delays, setups, holds, and samples. It also describes how to manipulate the vertical placement of a parameter, and how to change the transition attachments. These features allow you to control the information displayed and the appearance of the timing diagram.

The Advanced Modeling and Simulation Tutorial demonstrates how WaveFormer Pro can quickly model and simulate a digital system of moderate complexity. This tutorial will teach you how to model state machines using Boolean equations, use the Report window to find simulation errors, enter direct HDL code, model tristate gates, model n-bit gates, and call external HDL models. All WaveFormer and TestBencher Pro users should do this tutorial.

Specialized Feature Tutorials

Parameter Libraries covers the use of libraries and macro lists. This tutorial is important to do before starting a large project. Using Libraries and macro lists can save you a great deal of time if they are configured properly.

The Advanced HDL Stimulus Generation Tutorial covers the basic concepts of HDL stimulus generation, such as graphical waveform states, language-independent hexadecimal and binary bus translation, and user-defined types. WaveFormer Pro and TestBencher Pro users should do this tutorial.

Basic Verilog Simulation covers the basic simulation features of VeriLogger Pro. This tutorial also discusses how to create and manage projects, as well as how to build and simulate your design. VeriLogger Pro and TestBencher Pro users should perform this tutorial.

The Reactive TestBench Generation Tutorial introduces some of the optional reactive test bench features available with the Reactive TestBench Generation option. This option enables some of the diagram level capabilities that are available in TestBencher Pro - such as reactive Samples, diagram level User Defined Class Methods and much, much more. You may want to consider performing this tutorial if you are a TestBencher user to introduce you to some of the features available at the diagram level.

Test Bencher Pro Tutorials

TestBencher Pro: Basic Tutorial covers the basic concepts of using TestBencher Pro to generate bus-functional models for Verilog, VHDL, & OpenVera. It covers signal properties (type, direction, vector size, and bi-directional segments), samples, parameterized state values, end diagram markers, interface diagrams, modifying top-level template files, and generating test benches. TestBencher Pro users should do this tutorial.

TestBencher Pro: AMBA Example demonstrates how to create and use an AMBA AHB master. It makes extensive use of Pipeline Boundary Markers in the master transactors which are used to model the pipeline behavior defined by the AMBA specification. "Blocking Samples" in the master write and read transactions are used to wait for HREADY. Loop Markers in the master idle and busy transactors insert variable number of idle or busy cycles. State Variables and "Store Sampled Value As Subroutine Output" variables in the master write transactor are used to pass the read data back to the sequencer process. There is also a User-defined Class Method that determines the burst length based on a given burst code (defined by AMBA spec.). And finally the project makes use of Constrained randomization so that idle and busy transactors are applied using a random number of idle or busy cycles.

TestBencher Pro: PCI Example demonstrates how to create PCI master and PCI slave bus-functional models (BFMs) using TestBencher Pro. These are not 100% complete BFMs that can test every feature of the PCI protocol. Instead, they are just partial BFMs to help in the understanding of TestBencher Pro. Each BFM is modeled using a TBP project, which is then instantiated in another project named PCI.hpj. This an excellent example of hierarchical model design how the user can specify ports of slave and master BFMs using the Component Signals & Ports dialog. Some features used in this example include: loop markers, wait until markers, HDL code markers, state variables, simple expect samples, blocking & non-blocking samples, and user defined samples..

TestBencher Pro: Pipeline Example demonstrates how pipelined transactors can be created and how they work. To create the pipeline phases, "Pipeline Boundary" Markers were placed on each clock edge that starts and/or ends a pipeline phase. For each "Pipeline Boundary" Marker that starts a phase, a semaphore name is specified. This is done in the "Edit Marker" dialog and can be any valid identifier. To indicate the end of the last pipeline phase, you can either select "End Boundary" as the semaphore name or create an "End Diagram" marker.

TestBencher Pro: UART Example demonstrates how to design a Universal Asynchronous Receiver/Transmitter (UART) controller which is the key component in serial bus communications. The UART takes bytes of data and transmits the individual bits in a sequential fashion. At the destination, a second UART re-assembles the bits into complete bytes. This project contains three transactors: CLK_generator, WriteSerial, and ReadSerial. In this example, the WriteSerial and ReadSerial transactors communicate with each other. They send and receive serial data on a signal named UART. But, they work with parallel data at the transactor level. For example, the write transactor has an eight bit argument which it then converts to serial data. Both of these diagrams also have a parameter named "speed" which controls how many clock cycles are to be used for each bit of data.

TestBencher Pro: VME Example demonstrates how you would create bus-functional models (BFMs) for the arbiter, master, and slave VME components. It also shows one way to configure a set of slave BFM instances to respond to different address ranges. Each of these BFMs are represented by a TestBencher Pro project which are all instantiated in a top-level project named VME.hpj. This entire example is composed of unclocked diagrams.

Evaluators: If you are evaluating the product we recommend that you do at least the General Design tutorials. These will give you a good idea of the flexibility of the product. If you design in VHDL or Verilog you should also look at the HDL tutorial and the TestBencher tutorial and examples.